(A) Field of the Invention
The present invention is related to a non-volatile memory cell and the manufacturing method thereof, and more particularly to a vertical memory cell and the manufacturing method thereof.
(B) Description of the Related Art
With the development of high degree integration on a substrate, scaling down a non-volatile memory cell is rather hindered due to inherent dimensions of source, drain and gate channel thereof, so the roadmap of high density non-volatile memories may slow down significantly. Accordingly, the development of small memory cells is crucial for the next generation, and thus vertical memory cells have been attracting much attention recently.
Wong et al. disclosed a non-volatile memory cell of vertical floating gates in U.S. Pat. No. 5,739,567. FIG. 1 shows a vertical memory cell 500 disclosed by Wong et al., where channel regions 503 are formed on the top of a source region 502, and drain regions 504 are formed on the top of the channel regions 503. Floating gates 505 are formed on the sidewalls 506 of a trench 507. A gate dielectric film 508 is formed between the floating gate 505 and the source region 502, the drain region 504 as well as the channel region 503. A control gate 509 formed adjacent to the floating gate 505 in the trench 507 covers the floating gate 505. The control gate 509 is insulated from the floating gate 505 and the source region 502 by a layer of dielectric film 510. The cell 500 is programmed by conventional hot electron injection and is erased by electron tunneling from the floating gates 505 to either the source region 502 or the drain regions 504. The drain regions 504 and source region 502 are at different heights, and the gate dielectric films 508 are located vertically. Obviously, the gate channels do not occupy any space in the horizontal direction, so a high degree integration can be obtained.
Further, a conventional non-volatile memory cell normally needs high current to operate, e.g., 200 microamperes (μA), for hot electron programming, so it is not satisfactory for low power devices that comply with the tendency for chip development. Therefore, a split gate technology has been developed to obtain the high efficiency and low current programming, where the programming current can be diminished to, for example, 10 μA. In view of the consideration of a high degree integration and low power, the skill to integrate the vertical cell and split gate has come into existence.
For the concern of high power consumption during hot electron programming, as shown in FIG. 2, Wong et al. further disclosed a split gate architecture 900 in U.S. Pat. No. 5,386,132 to achieve the capability of low current programming. There are two transistors formed in series, where a transistor 921 is formed in a trench 907 and a transistor 922 is formed in another trench 920. In comparison with the conventional vertical memory cell 500 as shown in FIG. 1, the transistor 922 is integrated into the split gate cell structure by adding another trench 920 adjacent to the trench 907. The transistor 921 is the floating gate transistor with a channel length 912 determined by the edge of the drain 904 and the bottom of the trench 914 and with the channel width determined by the perimeter of the trench 907. A control gate 909 is insulated from a floating gate 905 and a channel region 903 by oxide layers 910 and 924, respectively, and gate dielectric films 908 are located vertically. The transistor 922 is the series select transistor with a channel length 923 determined by the distance between the bottom of trench 914 and source region 902, and with the channel width determined by the perimeter of the second trench 920. Accordingly, a second deep trench is formed to modulate a second portion of the channel and form a series transistor, which in fact leads to a rather complex process.
As shown in FIG. 3, Lin et al. disclosed a split gate memory cell of another type in U.S. Pat. No. 6,087,222. A memory device 100 is established in trenches of a substrate 101, in which the source region S and drain regions D are formed at different heights, and a tunnel oxide 102, a polysilicon layer 108, an oxide-nitride-oxide (ONO) layer 103 and another polysilicon layer 105 are sequentially formed. In addition, spacers 104 are formed beside the polysilicon layers 105. The polysilicon layers 108 and 105 act as a floating gate and a control gate, respectively. As a result, there are a series of transistors between the source region S and the drain region D. The control gate, i.e., the polysilicon gate 105, is operative to couple a voltage to the floating gate 108 in the light of a coupling ratio, and further acts as a split gate. However, the split gate voltage is not operated independently, despite the fact that the control gate voltage can turn on the floating gate and split gate transistors effectively, and electrons may jump into the floating gate as well as the control gate owing to high bias voltages generated both in the floating gate and in the control gate. Accordingly, although this approach may reduce process complexity, electron injection efficiency during programming may not be optimized. Since gate voltage of the select transistors is always coupled from control gate and cannot be independently adjusted, low programming efficiency or electrons trapped in the ONO layers may be created instead. Thus, it is necessary to develop a split gate vertical memory transistor with simple process and high programming efficiency.